1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, particularly to the uppermost layer interconnect and passivation structure thereof.
2. Description of the Related Art
Various kinds of techniques are known for planarizing an upper surface of interconnect the dielectric film that are employed between the metal layers, so-called intermetal dielectric, at manufacturing a semiconductor device of VLSI (Very Large Scale Integrated Circuit) and the like. The semiconductor device manufactured using the conventional technique planarizing interconnect dielectric is shown in FIG. 6.
According to the conventional method for manufacturing, first, an object forming field oxide film 2 on a semiconductor substrate 1 is prepared and a MOSFET (Metal-Oxide-semiconductor Field Effect Transistor) having a poly silicon gate 5 is formed on the field oxide film 2 and semiconductor substrate 1 as shown in FIG. 6.
Next, ILD (Inter Layer Dielectric) 3 is formed so as covering them. The inter layer dielectric 3 consists of PSG (Silicon oxide doping Phosphorus) or BPSG (Silicon oxide doping Boron and Phosphorus). Next, aluminum interconnect 4 is formed on the inter layer dielectric 3.
By depositing USG (Silicon glass not doped) using CVD method (Vapor phase epitaxy method) and the like, USG layer 6 is formed.
Next, after forming aluminum interconnect 7s as the uppermost layer metal interconnect, and forming passivation film and PSG (Silicon oxide doping Phosphorus) or BPSG (Silicon oxide doping Boron and Phosphorus) 8, SOG film 8s is formed so as to planarized surface.
Thus, although planarizing of the surface is carried out with forming the passivation film, there are problems that passivation film of enough film thickness must be formed to protect completely aluminum interconnect of foundations and that it takes time for forming film.
Moreover, bonding is need for the uppermost layer interconnect and it needs to form an electrode pat superior in bonding resist. Therefore, it is need that only a part of the bonding pad is formed separately or that thickness of film is made thick enough at the case forming it on the same process. Therefore, roughness of the surface is made large, so there is a problem that planarizing process of the passivation film forming on the upper layer is difficult.
Further more, in the SOG process, many process and operations are need. For example, before removing unnecessary part by etching-back after applying SOG layer, measuring process of thickness of film of the applied SOG layer and annealing process of the applied SOG layer, and in the etching-back process of the SOG layer, operation of measuring thickness of the remained film is need. Moreover, after the etching-back process, O2 plasma processing process, scrubber process using a brush, and so on are need. Further more, although silicon compound (generally RnSi(OH)4-n) is used for insulation material, there is a problem that it is comparatively expensive.
As described above, in the conventional interconnect structure, there are problems such that manufactureability is low or it is difficult to keep reliability.